Title: Introduction to the AI Engine and to its Programming Model

  • Date: 11th Dec. 2023, 13:30-17:00 (JST)
  • Organizer: Vicky Chen (AMD University Program); Joshua Lu (AMD University Program)
  • Abstract: This tutorial will primarily focus on the Adaptable Intelligent Engine (AIE), a new type of compute element. We will describe the AI Engine tile and AI Engine array architecture as well as the different data movement alternatives. A project-based learning lab will be provided to attendees for the hands-on experience of using AI Engine to accelerate the DSP algorithm. In the meantime, the latest Ryzen AI design flow, new Vitis IDE and HLS code analyzer features in 2023.2 release will be demonstrated during this tutorial.
  • For more detail: Please check and register at the AMD's tutorial page. Registration is recommended.
  • Place: Yokohama Landmark Tower, 25th floor, 2 Chome-2-1 Minatomirai, Nishi Ward, Yokohama, Kanagawa 220-8125, Japan (10 mins walk from the conference venue.)


Title: Intel® FPGA AI Suite and AI Tensor Blocks: Empowering Real-time, Low-Latency, and Low-Power Deep Learning Inference with Intel FPGAs

  • Date: 14th Dec. 2023, 14:00-15:30(JST)
  • Organizer: Jahanzeb Ahmad (Sr. Solutions Architect, Intel Programmable Solutions Group)
  • Abstract: This hands-on tutorial presents the Intel FPGA AI Suite and groundbreaking AI Tensor Blocks newly integrated into Intel’s latest FPGA device families for deep learning inference. These innovative FPGA components bring real-time, low-latency, and energy-efficient processing to the forefront, supported by the inherent advantages of Intel FPGAs, including I/O flexibility, dynamic reconfiguration, and long-term support. We delve into the Intel FPGA AI Suite, demonstrating its flexibility in achieving scalable performance and seamless integration with industry-leading frameworks like TensorFlow and PyTorch, facilitated by Quartus Prime Software. Moreover, we highlight the game-changing role of AI Tensor Blocks in enhancing deep learning inference performance. This tutorial offers both theoretical insights and practical experiences, equipping participants to leverage these advancements and revolutionize FPGA-based AI applications.
  • For more detail: You can jump into the tutorial without registration.
  • Place: Room 411+412, PACIFICO YOKOHAMA Conference Center 4th Floor (The same floor as the conference venue)